Complementary metal-oxide-semiconductor (CMOS) is a technology for constructing integrated circuits via semiconductors. CMOS technology is used to fabricate microprocessors, microcontrollers, static random access memory (RAM), and other digital logic circuits. CMOS technology is also used for several analog circuits such as image sensors (CMOS sensor), data converters, and highly integrated transceivers for many types of communication applications. The word “complementary” refers to the fact that the typical design style with CMOS uses complementary and symmetrical pairs of p-type and n-type metal oxide semiconductor field effect transistors (MOSFETs) for logic functions. The phrase “metal-oxide-semiconductor” is a reference to the physical structure of certain field-effect transistors, having a metal (or doped polycrystalline silicon) gate electrode placed on top of an oxide insulator (e.g., silicon dioxide), which in turn is on top of an n-type or a p-type semiconductor material.
CMOS technology in the past decade has made great progress in reaching the terahertz (THz) threshold. Significant advancements have been made on the reception front with passive detection reaching 10 THz. Efficient and broadband signal generation beyond 300 gigahertz (GHz) in a compact form factor, however, remains a challenge due to limited transit-time and device parasitics that lead to high frequency performance roll-off and place limits on maximum operating frequencies.
Oscillators incorporating a frequency multiplication function allow for frequencies above traditional maximum frequencies of a device. The major drawback of such circuits is low realized bandwidths at high frequencies making them unattractive for many applications. Another technique is harmonic multiplication through nonlinear mixing using an input driving signal at relatively low frequencies. Active multipliers, although promising, consume direct current (DC) power and suffer from excessive resistive loss above maximum oscillation frequency of the device (fmax) leading to poor efficiency. Accumulation-mode MOS (A-MOS) and Schottky-barrier diode (SBD) varactors have been used previously to implement passive frequency-doublers with output frequency at 125 GHz and 480 GHz, respectively with acceptable efficiency and output power (POUT). While promising, these passive doublers suffer from multiple limitations, including: 1) low-order multiplication requires a high power amplifier (>10 decibel milliwatts (dBm)) near technology fmax to drive the circuit, which is either non-realizable or extremely inefficient in area and power; 2) higher-order multiplication using predominantly square-law A-MOS varactors necessitates idlers for secondary mixing leading to poor conversion loss (CL) performance—due to loss in passive-idlers and due to the indirect nature of mixing—and introducing bandwidth reductions on the system since the idlers are tuned elements; and 3) unavoidable harmonics are suppressed by use of on-chip baluns and symmetric-ring combining structures leading to bandwidth limitation and loss.